1. Field of the Invention
The present invention relates to a method of inspection of a semiconductor memory device, and is mainly directed to a method of inspection suitable for tests during the overall production of a semiconductor memory device and is applicable to general semiconductor memory devices.
2. Description of the Prior Art
With a variety of technical advances in semiconductor memory devices, the demand for semiconductor memory devices is increasing. Because of various use demands, it is important to shorten the period of development of a semiconductor memory device. In general, in the development of the semiconductor memory device, the design and manufacture take a period of about three months. Defects in design, especially in wiring, and defects in characteristics are inevitable in a product thus developed. Inspections for detecting defects are therefore carried out. The inspections are made not only for wiring checks, but naturally include tests on characteristics, such as supply voltage fluctuation tests, temperature tests, clock timing tests and cross-talk tests. Since the results of the tests are judged through write-in and read-out operations, defects in wiring particularly produce the same test result as does any other defect. Accordingly, the analysis of the defects becomes extremely complicated. It will be understood, in view of the above-mentioned period of development, that the precision of defect analysis greatly affects the period for developing a new product.
Since the semiconductor memory device has a large memory capacity amounting usually to 1 K-bits or greater to 2 K or 4 K bits, the write-in or read-out pattern for the inspection is massive. The pattern has hitherto involved continuous and repeated operations of several tens of program steps. It has, therefore, been impossible to prepare and use different test patterns for the respective defects. As a consequence, it has been unavoidable that the same defective part is detected over and over.
An example of the above-mentioned prior art type of inspection technique and an apparatus for accomplishing the same is illustrated in FIG. 3 of the drawings. This apparatus is commercially available and may be a Doctor -32 Memory Tester, manufactured by Adar Co. With reference to the drawings, a semiconductor memory device 1 includes a pair of decoders 3 and 4 for accessing a memory cell part 2. This is accomplished by the use of a microprogram part 7 which is connected by way of X-counter 5 and Y-counter 6 to the respective decoders 3 and 4. The microprogram part 7 provides a test pattern to be used in testing the memory cells.
As each semiconductor memory cell is accessed and tested, whether or not the same is a satisfactory cell or a defective one is judged by a judging part 12. The output of the judging part 12 is applied to one input terminal of AND gate 11. To another input of the gate timing pulses are supplied for gating out the output of the judging part 12 in accordance therewith to a fail memory 13.
In operation, during the inspection of one of the characteristics of the memory cell, for example, the inspection of the wiring thereof, let it be assumed that one of the cells has defective wiring so that the judging part 12 will provide a "1" level indicating a defective cell.
Now, with reference to FIG. 4, which illustrates the relationships between various signals supplied to the gate 11 and the output therefrom in the device shown in FIG. 3, where a particular cell has been detected to be defective, represented by a "1" signal, a signal A corresponding thereto, provided at the output of the judging part 12, indicates the same. With the coincidence of the timing pulse supplied to the other input of the gate 11 with the "1" level of signal A, for the particular memory cell being tested, the output of the gate 11 at that particular time will be a "1" as shown by signal D.
On the other hand, for a memory cell which passes the test involved such as the wiring test referred to above, the output of the judging part 12 will have a signal level "0" indicating a "good" or "acceptable" cell, so that for the synchronizing signal corresponding in time with that particular output, the AND gate 11 will receive a "0" and a "1" input simultaneously, so that its output will be a " 0".
Thus, as each of the cells is tested and the judging part provides an output of the results of the tests, the fail memory 13 will be supplied with signals representative of the results of the tests for each respective cell, in synchronism with the timing pulses, for every test which is run on the cells. This means that where a plurality of testing operations are conducted for the memory cells, signals representative of the tests for each of the cells will be supplied to the fail memory 13.
One of the problems with this type of system is the fact that if, during an initial test, a cell has been found to be defective, it is still subsequently tested and the results thereof supplied to the fail memory for each of the subsequent tests thereby considerably complicating the process; also, additional time and storage space in the fail memory is required.